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HD74CDC857
3.3/2.5-V Phase-lock Loop Clock Driver
ADE-205-222E (Z) 6th. Edition July 1999 Description
The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
* Supports 100 MHz to 150 MHz operation range *1 * Distributes one differential clock input pair to ten differential clock outputs pairs * SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input * Supports spread spectrum clock * External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input * Supports both 3.3 V/2.5V analog supply voltage (AV CC), and 2.5 V VDDQ * No external RC network required * Sleep mode detection * 48pin TSSOP (Thin Shrink Small Outline Package) Note: 1. 200 MHz (Max) ver. will be available by 4Q/'99
Function Table
Inputs G L L H H X H: L: Z: X: CLK L H L H 0 MHz CLK H L H L 0 MHz : : : : : : : Outputs Y Z Z L H Z Y Z Z H L Z FBOUT Z Z L H Z FBOUT Z Z H L Z : : : : : off off run run off : PLL
High level Low level High impedance Don't care
HD74CDC857
Pin Arrangement
GND 1 Y0 2 Y0 3 V DDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 V DDQ 11 V DDQ 12 CLK 13 CLK 14 V DDQ 15 AV CC 16 AGND 17 GND 18 Y3 19 Y3 20 V DDQ 21 Y4 22 Y4 23 GND 24
48 GND 47 Y5 46 Y5 45 V DDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 V DDQ 37 G 36 FBIN 35 FBIN 34 V DDQ 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 V DDQ 27 Y9 26 Y9 25 GND
(Top view)
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HD74CDC857
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage
*1
Symbol VDDQ VI VO I IK I OK IO
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDDQ +0.5 -50 -50 50 100 0.7
Unit V V V mA mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current
VI < 0 VO < 0 VO = 0 to VDDQ
Supply current through each V DDQ or GND I VDDQ or IGND Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Tstg
-65 to +150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
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HD74CDC857
Recommended Operating Conditions
Item Supply voltage Symbol AVCC AVCC Output supply voltage DC input signal voltage High level input voltage Low level input voltage High level input voltage Low level input voltage Differential input signal voltage
*2 *1
Min 2.3 3.0 2.3 -0.3
Typ -- -- -- -- -- -- -- -- -- -- -- 1.25 -- -- -- --
Max 2.7 3.6 2.7 VDDQ+0.3 -- 0.8 VDDQ+0.3 0.7 VDDQ+0.6 VDDQ+0.6 0.5xVDDQ +0.35 1.35 -30 30 -- 70
Unit Conditions V f CLK = 100 to 150 MHz f CLK = 130 to 150 MHz V V V V V V V G input pin G input pin DC AC V V mA Vref = 0.5 x V DDQ All pins
(1) (2)
VDDQ
VIHD VILD VIHG VILG VID
1.7 -- 1.7 -0.3 0.36 0.7
Differential cross point voltage Reference voltage Output current
*4
*3
0.5xVDDQ -0.35 Vref I OH I OL 1.15 -7 7 1 0
Input slew rate Operating temperature Notes: 1. 2. 3. 4.
SR Ta
V/ns C
Unused inputs must be held high or low to prevent them from floating. Feedback inputs (FBIN, FBIN) may float when the device is in low power mode. DC input signal voltage specifies the allowable dc execution of differential input. Differential input signal voltage specifies the differential voltage |VTR-VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. Differential cross point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. (See figure1-1) Vref is the reference DC level, when using single clock input. When CLK (pin#13) is single ended input, CLK (pin#14) must be set Vref . (See figure1-2)
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HD74CDC857
VDDQ VTR VCP GND Crossing point VID
Figure 1-1 Differential input levels
VDDQ CLK CLK Vref
*4
CLK CLK Vref
GND
Figure 1-2 Single input levels
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HD74CDC857
Logic Diagram
G
Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 PLL Y8 Y8 Y9 Y9 FBOUT FBOUT
CLK CLK FBIN FBIN
AVCC
Note: All inputs and outputs are associated with VDDQ = 2.5 V.
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HD74CDC857
Pin Function
Pin name AGND AVCC No. 17 16 Type Description Ground Analog ground. AGND provides the ground reference for the analog circuitry. Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AV CC can be used to bypass the PLL for test purposes. When AV CC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Clock input. CLK provides the clock signal to be distributed by the HD74CDC857 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Output bank enable. G is the output enable for all outputs. When G is low, VCO will stop and all outputs are disabled to a high impedance state. When G will be returned high, PLL will resynchroniz to CLK frequency and all outputs are enabled.
CLK, CLK
13, 14
I
FBIN, FBIN
35, 36
I
FBOUT, FBOUT 32, 33
O
G
37
I
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48 4, 11, 12, 15, 21, 28, 34, 38, 45
Ground Ground
VDDQ
Power
Power supply
Y
3, 5, 10, 20, O 22, 27, 29, 39, 44, 46 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 O
Clock outputs. These outputs provide low-skew copies of CLK.
Y
Clock outputs. These outputs provide low-skew copies of CLK.
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HD74CDC857
Electrical Characteristics
Item Symbol Min -- Typ *1 -- Max -1.2 -- -- -- 0.2 0.35 0.55 10 4 A pF Unit V V Test Conditions I I = -18 mA, VDDQ = 2.3 V I OH = -100 A, VCC = 2.3 to 2.7 V I OH = -8 mA, VCC = 2.3 V I OH = -16 mA, VCC = 2.3 V I OL = 100 A, VCC = 2.3 to 2.7 V I OL = 8 mA, VCC = 2.3 V I OL = 16 mA, VCC = 2.3 V VI = 0 V to 2.7 V, VDDQ = 2.7 V VIK Input clamp CLK, CLK voltage FBIN, FBIN, G Output voltage VOH
VCC-0.2 -- 1.95 1.70 -- -- -- -- -- -- --
VOL
-- -- --
Input current Input capacitance Note:
II CI
-- --
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Switching Characteristics
Item Cycle to cycle jitter Phase error time Output skew Differential clock skew Duty cycle Output impedance Clock frequency ZO f CLK t (phase error) t sk (o) t sk (diff) Symbol Min -100 -150 -- -100 45 -- 100 130 Slew rate Stabilization time Note: 1.2 -- Typ -- -- -- -- -- 25 -- -- -- -- Max 100 150 200 100 55 -- 150 150 -- 0.1
*1 *1
Unit Test Conditions ps ps ps ps % See figure 2 See figure 2, 3, 4 See figure 2 See figure 2 See figure 2 See figure 2
MHz See figure 2, AV CC = 2.50.2 V See figure 2, AV CC = 2.50.2 V or AV CC = 3.30.3 V V/ns See figure 2 ms See figure 2, 3
1. 200 MHz (Max) ver. will be available by 4Q/'99.
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HD74CDC857
Differential clock outputs are directly terminated by a 120 resistor. Figure 2 is typical usage conditions of outputs load.
V DDQ Device under OUT test
V DDQ
RT = 120
OUT
Figure 2 Differential signal using direct termination resistor
Differential cross point voltage
V IH V ref +0.35 V V ref V ref -0.35 V V IL
Vref VIH VIL
0.5 x VDDQ 1.7 V 0.8 V
Figure 3 CLKIN waveforms
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HD74CDC857
CLKIN (Differential input)
FBIN t(phase error)
CLKIN (Single input)
Vref
FBIN t(phase error)
FBOUT
Yx tsk(o)
Yx
Yx' tsk(o)
Yx
Yx tsk(diff)
Figure 4 Timings
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HD74CDC857
Package Dimensions
Unit : mm
12.50 -0.1 48
+0.3
25 6.10 +0.3 -0.1
1 0.20 +0.1 -0.05
0.50 0.08 M 0.65 Max
24 0.15 0.05
8.10 0.3 10 Max 0.50 0.1 Hitachi code EIAJ code JEDEC code TTP-48DC -- --
0.10
1.20 max
0.05 Min
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HD74CDC857
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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